We will exhibit at NEPCON JAPAN 2024 that will be held in January 24th-26th, 2024 at TOKYO BIG SIGHT.
In our booth, some wafer sample works will be displayed that PMT Package Foundry produced. In addition to sample of 1inch wafer, 6inch one is also displayed.
Please feel free to visit our booth!
Contents of Display
FOWLP（Fan-Out Wafer Level Package）
Package substrate, wire bonding, or solder bumps are not required for FOWLP structure, and it allows reducing size and profile in comparison with FCBGA structure.
Forming multi RDL on Al pad on IC chip by using both lithography and plating technology allows more flexible RDL design than conventional package.
Furthermore, heat consumption can be improved because thickness of package will be thinner to almost 100µm.
Details of Exhibition
Date: From January 24th (Wed) to 26th (Fri)
Displayed Contents: Sample works of 1 inch or 6 inch wafer that PMT Package Foundry produced
Venue: TOKYO BIG SIGHT (Ariake, Koto-ku, Tokyo, Japan)
Booth: No. E19-16 (Located between East Hall-2 and 3)
Entrance Fee: Free (Visitor is required registration beforehand from official website)
Official Website: https://www.nepconjapan.jp/tokyo/en-gb.html
PMT Package Foundry is a foundry service specializing in small volume manufacturing of FOWLP (Fan-Out Wafer Level Package) and WLCSP (Wafer Level Chip Size Package).
We fabricate Cu rewiring packages utilizing semiconductor front-end process and plating technology.
We support customers' PoC (Proof of Concept) for chip development and product development.
Details of PMT Package Foundry can be shown from following link>> Package Foundry