What is Package Foundry
Package Foundry is a foundry service specializing in small volume manufacturing of FOWLP (Fan-Out Wafer Level Package) and WLCSP (Wafer Level Chip Size Package).
We fabricate Cu rewiring packages utilizing semiconductor front-end process and plating technology.
In addition to silicon, we also have experience in packaging compound semiconductors such as SiC and GaN.
Vision of PMT Package Foundry
PMT Package Foundry is a package contract manufacturer specializing in FOWLP prototyping, established in 2019 as a new business in PMT. We are striving to develop technologies to help solve our customers' problems in a short period.
We support customers' PoC (Proof of Concept) for chip development and product development, and in 2022, we are expanding to not only prototype development of packages but also high-mix low-volume production in cooperation with Maxell, Ltd. in Fukuoka Prefecture.
Delivery time and Price
There is no need to supply wafers in units as we can make solder bump on IC chips that diced into small pieces.
We may offer competitive prices and shorter delivery times compared to overseas OSATs and semiconductor laboratories.
Design and Verification
PoC of the designed IC chips by package with rewiring (RDL).
Functional verification of heterogeneous packages (SiP) that combine multiple IC chips with different functions.
No package substrate or bumps are required, enabling a low profile package. The lower profile can be expected to reduce thermal resistance and improve heat dissipation.
In addition, it should make a reduction in electrical resistance of wiring and improvement in signal noise can be expected.
We help our customers solve their problems by integrating wafer front-end process, packaging process, and plating process.
Package Structure Comparison
Package substrate, wire bonding, or solder bumps are not required for FOWLP structure, and it allows reducing size and profile in comparison with FCBGA structure.
Forming multi RDL on Al pad on IC chip by using both lithography and plating technology allows more flexible RDL design than conventional package.
Furthermore, heat consumption can be improved because thickness of package will be thinner to almost 100µm.
|Production Line||1 or 6 inch production line (Prototype, High-mix Low-volume Production, Multi-layer RDL)|
|Package Type||FOWLP, WLCSP, SiP (System-in-Package), DSEP (Double-sided Electrode Package), AiP (Antenna-in-Package), Ultra-thin Package|
|Bump||Cu Pillar Bump, Cu Pad, Solder Bump|
Fan-Out Wafer Level Package (FOWLP)
RDL interposer is connected to the input/output pads of the IC chip, and it allows connecting to any position on the board.
Heat dissipation can be expected to be improved due to miniaturization or lower profile.
Wafer Level Chip Scale Package (WLCSP)
Package size of WLCSP is same as mounted semiconductor chip.
Solder bumps can be formed on IC chips that is diced into small pieces by using shuttle service.
System in Package (SiP)
Systematization of multiple ICs with different functions in a single package make it high functionality and space saving in the package.
Power consumption is expected to reduced because mounting area becomes smaller.
Double-sided Electrode Package (DSEP)
The I/O signals of the IC chip can be connected from the front side and back side of the package.
High functionality can be achieved by stacking packages.
*Package on Package (Stacking IC Package) is not our business.
The package is made thinner to 100µm to facilitate heat dissipation and prevent heat retention inside the package.
This package is also suitable for wearable modules that ultra-thin shape is required, such as medical devices.
Antenna in Package (AiP)
Utilize multi-layer RDLs to integrate the antenna structure into the package.
Conventionally, antenna element used to be connected separately.
Antenna structure can be built in package by utilizing multi layer RDL, and this technology allows miniaturization of RF (high-frequency) device package.
Antenna shapes are available upon customer’s requirement.
This technology can be applied to RF device more than several hundred GHz.
Cu Pillar Bump
In addition to Cu pad or solder bump, Cu pillar bump of dia. 40µm x (t=)40µm can be formed.
In the midst of the growing need toward increasing number of terminals due to high-integration of package, this can meet the request of narrow pad pitch.
This is package structure incorporating semiconductor chip or sensor.
KGD (Known Good Die) can be provided without solder bump. Both solder ball and Cu pad are available for external terminal.
(*)Dia. 150mm will be released in 2023/4Q.
FOWLP Process Flow
Our baseline process is face-down chip-first.
When you need face-up chip-first, RDL-first or other specific process options, please feel free to contact us.
Reconstruction Wafer Process
Rearranging Si die on carrier substrate and curing with resin.
After that, peeling off carrier substrate.
Constructing redistribution layer (RDL) by patterning dielectric layer (DL) and Cu RDL.
Solder-ball Mounting Process
Constructing upper dielectric layer(DL-2) and UBM Layer, and mounting solder ball on it.
Deliver singulated package by dicing.
- Customers provide us with requirement specifications, RDL CAD, and IC chips.
- We design the process according to the design rule.
- Packages are fabricated and deliver them to customers.
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